Embodiments of this disclosure relate to a nonvolatile memory device and, more particularly, to a three-dimensional (3-D) nonvolatile memory device and a method of manufacturing the same, and a memory system including the 3-D nonvolatile memory device.
In order to increase the degree of memory devices, a 3-D structured memory device in which memory cells are arranged in a 3-D has been proposed. The 3-D structured memory device can efficiently utilize the area of a substrate and improve the degree of integration as compared with the case where memory cells are arranged in a two-dimensional. In particular, it has been suggested that the regular arrangement of the memory cells of a NAND flash memory device, which is advantageous to the high degree of integration as one of nonvolatile memory devices, is applied into a 3-D structure.
A 3-D memory device includes strings having memory cells stacked over a substrate and select transistors. The channel of the string is formed along vertical channel layer protruded upwardly from the substrate. The gates of the memory cells are formed to surround the vertical channel layer. An interlayer insulating layer is formed between the gates of memory cells in adjacent layers. The gate of the select transistor is formed to surround the vertical channel layer. The gate of the select transistor is spaced apart from the gates of the memory cells with the interlayer insulating layer interposed between the select transistor and the memory cells.
The vertical channel layer may be formed within a vertical hole that penetrates the interlayer insulating layers and conductive layers. The interlayer insulating layers and the conductive layers are alternately stacked. The conductive layers are used as the gates of the memory cells and the gate of the select transistor. Before forming the vertical channel layer, a multi-layered layer including a charge blocking layer, a charge trap layer and a tunnel insulating layer, which are sequentially stacked, is formed on the sidewall of the vertical hole. In this case, when the select transistor is operated, charges are trapped in the charge trap layer of the select transistor because the charge trap layer is formed between the gate of the select transistor and the vertical channel layer. As a result, the threshold voltage of the select transistor may shift. In particular, in the 3-D memory device, an erase operation is performed using Gate Induced Drain Leakage (GIDL) current induced by generating holes on the select gate side. If voltage supplied to the select gate is raised in order to increase the erase speed of this 3-D memory device, the threshold voltage of the select transistor further greatly shifts because the amount of charges trapped in the charge trap layer of the select transistor increases.
Meanwhile, the vertical channel layer may have a stack structure of a first vertical channel layer and a second vertical channel layer. The first vertical channel layer is formed within a first vertical hole that penetrates the interlayer insulating layers and the conductive layers used as the gates of the memory cells. The interlayer insulating layers and the conductive layers are alternately stacked. Before forming the first vertical channel layer, a multi-layered layer including a charge blocking layer, a charge trap layer and a tunnel insulating layer, which are sequentially stacked, is formed on the sidewall of the first vertical hole. The second vertical channel layer is formed within a second vertical hole through which the top surface of the first vertical channel layer is exposed. The second vertical hole is formed to penetrate a conductive layer for a select gate additionally deposited after forming the first vertical channel layer. Before forming the second vertical channel layer, a gate insulating layer is formed on the sidewall of the second vertical hole. In this case, a shift in the threshold voltage of the select transistor when the select transistor is operated may be improved because the charge trap layer is not formed between the gate of the select transistor and the second vertical channel layer.
In the process of forming the gate insulating layer on the sidewall of the second vertical hole, an insulating layer is deposited on the entire structure including the second vertical hole. The insulating layer is partially etched to expose the top surface of the first vertical channel layer. Here, a problem may arise because the first vertical channel layer is damaged by the etch process of the insulating layer.
Meanwhile, in the process of forming the second vertical channel layer within the second vertical hole, a semiconductor layer is deposited on the entire structure including a gate insulating layer. The semiconductor layer out of the second vertical hole is removed. Here, a concern arises because the gate insulating layer of the select transistor may be damaged by the etch process of the semiconductor layer.
As described above, in the known 3-D memory device, it may be difficult to secure operation reliability because of the concern related to shifting of threshold voltage of the select transistor or the concern related to damage in the gate insulating layer and the channel of the select transistor.